1. Technical Field
The present invention is directed to a semiconductor memory device; in particular, a DRAM having a segmental cell array.
2. Discussion of the Related Art
Generally, a DRAM read/write operation involves three commands—an active command to select a row address and a word line, an RD/WR command (a read command or a write command) to select a bit line and a column address, and a precharge command to complete read/write operation and prepare a next read/write operation.
To achieve high-speed data transfer rate, the recent trend in the DRAM industry has focused on improvements in interface performance, and generally not on any changes in the DRAM core. As a result, the memory access time tRC has not greatly improved, and effective bandwidth falls steeply when the row address changes frequently. The practice of dividing a memory array into multiple banks (multi-bank approach) may improve the performance somewhat, but the problem of address transition within the same bank can cause fatal performance degradation.
A fast cycle random access memory (FCRAM) has been proposed for reducing tRC time. In a FCRAM, a memory cell array is segmented into a plurality of smaller blocks and each block is activated independently. In the segmented block, the number of cells connected to one word line could be reduced so that the activation time of a selected word in the block could be reduced.
FIG. 1 is a plan view illustrating a pin configuration of a conventional fast cycle dynamic semiconductor memory device. The fast cycle dynamic semiconductor memory device of FIG. 1 includes a power voltage pin VCC, a ground pin GND, address pins A1 to A12, block address pins A13 and A14, a bank address pin B0, data I/O pins DQ1 to DQ8, and command pins CMD. The command pins CMD are to apply a clock signal CLK, an inverted chip selecting signal CSB, and a signal FN.
When a read/write command is applied to the command pin CMD, the semiconductor memory device of FIG. 1 receives a row address via the address pins A1 to A12, a bank address via the bank address pin B0, and a block address signal via the block address pins A13 and A14.
When a lower address latch command signal is applied to the command pin CMD, the semiconductor memory device of FIG. 1 receives a column address signal via the address pins A1 to A10, an auto pre-charge control signal via the address pin A12, and a bank address signal via the bank address pin B0.
FIG. 2 is a block diagram of a conventional fast cycle dynamic semiconductor memory device. The conventional fast cycle dynamic semiconductor memory device includes two memory cell array banks 30-1 and 30-2, each including four memory cell array blocks 31-1 to 31-4, a command buffer 32, a command decoder 34, a bank address buffer 36, a row address buffer 38, a pre-charge control signal generating circuit 40, a block address buffer 42, a block selecting signal generating circuit 44, a column address buffer 46, row decoders 48-1 and 48-2, and column decoders 50-1 and 50-2.
The bank select circuit 36 buffers the bank address B0 in response to the ACTIVE command and RD/WR command to generate bank select signals BA and BB. The bank select circuit 36 selects the bank to be activated during row address buffer time in response to the active command and selects the bank for read/write operations during column address buffering in response to the RD/WR command.
The row-address buffer 38 buffers the addresses A1 to A12 in response to the ACTIVE command. The row decoders 48-1 and 48-2 decode the buffered row address outputted from the row address buffer 38 to generate the word line selecting signals WLl to WLm in response to the bank selecting signals BA and BB outputted from the bank address buffer 36, respectively.
The block address buffer 42 buffers the block addresses A13 and A14 in response to the ACTIVE command. The block selecting signal generating circuit 44 decodes the buffered block address outputted from the block address buffer 42 to generate the block selecting signals BK1 to BK4 in response to the ACTIVE command. Therefore, a Row or word line in a block cell array is activated by ACTIVE command along with bank address signal of pin B0, row address signal A1˜A12 of pin A1˜A12 and block address signal of pin A13˜A14. The column-address buffer 46 buffers the addresses A1 to A10 in response to the READ command. The column decoders 50-1 and 50-2 decode the column address to generate column selecting signals Y1 to Yn in response to the bank selecting signals BA and BB outputted from the bank address buffer 36, respectively.
The pre-charge control signal generating circuit 40 generates the auto precharge control signals PREA and PREB to perform a precharge operation of the memory cell array bank 30-1 and the memory cell array bank 30-2, respectively in response to the auto precharge command. The auto precharge command is issued at the same time with the READ command by bringing A12 to a logic “high.” Once the auto precharge command is given, no new commands are possible to that particular bank during the auto precharge operation. Thus, even if a memory access of data located at the same row address but a different block address, the precharge command being at high prevents overlapping operations. In other words, assume that two operations are in the same row address but different block addresses, prior to the termination of current operation by the precharge command, the memory controller cannot start a new operation. Therefore, a new active command for the second operation in activating a new block row address is issued only after the first operation is completed. Thus, the advantages of dividing the cell array into a plurality of the block cell arrays is reduced or eliminated.
U.S. Pat. No. 6,108,243 describes in detail the semiconductor memory device of FIG. 2.
FIG. 3 is a timing diagram illustrating a read operation of the semiconductor memory device of FIG. 2 when the memory cells located at the same row address but a different block address are successively accessed to the same memory cell array bank, wherein a burst length is 2, and a column address strobe (CAS) latency is 2.
In FIG. 3, CLK denotes a clock signal, and CMD denotes a command. B0 denotes a bank address. A1 to A11 denote a row address when the active command is applied and a column address when the read command is applied. A12 denotes a row address when the active command is applied and a pre-charge control signal when the read command is applied. DQ denotes a data output signal, and A13 and A14 denote block addresses.
FIG. 4 shows a simplified block diagram version of the memory cell array block according to the timing diagram of FIG. 3.
A successive read operation of the memory cell of the semiconductor memory device of FIG. 2 having the same row address and the different block address is described below with reference to FIGS. 3 and 4.
All of the read command RDA and all of the lower address latch command LAL are inputted at a rising edge of the clock signal CLK. In the first read operation, when the bank address BA, the row address RA1, and the block address BK1 are applied together with a first read command RDA, a word line {circle around (1)} of the memory cell array block 31-1 of the memory cell array bank 30-1 is selected.
When the bank address BA, the column address CA1 and the auto pre-charge control signal A12 having a logic “high” level are applied together with the lower address latch command LAL, a bit line {circle around (2)} of the memory cell array bank 30-1 is selected. Therefore, data is read from the memory cell MC1 between the word line {circle around (1)} and the bit line {circle around (2)}. And, a pre-charge operation of the memory cell array bank 30-1 is performed in response to the auto pre-charge control signal A12 having a logic “high” level.
The succeeding second read operation should be initiated after finishing the precharge operation. When the bank address BA, the row address RA2, and the block address BK3 are applied together with a second read command RDA, a word line {circle around (3)} of the memory cell array block 31-3 of the memory cell array bank 30-1 is selected.
When the bank address BA, the column address CA1 and the auto pre-charge control signal A12 having a logic “high” level are applied together with the lower address latch command LAL, a bit line {circle around (4)} of the memory cell array bank 30-1 is selected. Therefore, a data is read from the memory cell MC2 between the word line {circle around (3)} and the bit line {circle around (4)}. And, a pre-charge operation of the memory cell array bank 30-1 is performed in response to the auto pre-charge control signal A12 having a logic “high” level. Data QA11, QA12, QA21 and QA22 are outputted, in response to each read command RDA to a memory controller (not shown) two at a time in sequence when two cycles pass after the read command RD is applied. The memory controller waits for a given time period (“time gap”) to retrieve data QA21 and QA22 of the second read operation after it receives the data QA11 and QA12 of the first read operation.
Accordingly, it is desirous to maintain the advantages of segmenting the cell array into a plurality of the block cell arrays and increase system performance by a gapless operation for successively accessing memory cells having the same row address but different block addresses.